Abstract: Due to the low power consumption, CMOS structures are preferred for creating large and ultra-large integrated circuits. However, the reliability of the circuits is largely limited by the latch phenomenon that occurs in CMOS structures. The electrical characteristic of the latch up phenomenon in a CMOS integrated circuit is characterized by the presence of a number of anomalous phenomena. These effects distort and make ambiguous the results of measuring the electrical sensitivity of the circuits to the latch. The development of microelectronics is constantly striving to reduce the size of the elements of integrated circuits, in particular transistors. Reducing the size of integrated circuits leads to the amplification of short-channel effects in MOS transistors. When reducing the size of integral elements, various options for scaling devices with a metal-oxide-semiconductor structure are considered. The mechanisms that cause the appearance of the snap-in do not depend on the conductivity type of the semiconductor region of the pocket.